Tape Automated Bonding (TAB) is a widely used technique for packaging and mounting semiconductor devices. TAB has several desirable characteristics which make it attractive to semiconductor manufactures. For instance, TAB permits highly automated manufacturing and is suitable for use in high lead count semiconductor devices. In addition, TAB technology helps to keep device size to a minimum, whereas other packaging technology adds significant bulk to the device.
A typical TAB leadframe includes a pattern of metal leads formed on an insulating carrier tape. The carrier tape is most often a polymer, such as a polyimide or polyester. The metal leads are formed by patterning a thin metal foil, usually copper, using conventional lithography and etching procedures or by additive plating processes. Portions of the polymer tape are then removed to create free-standing portions of the leads which are subsequently bonded to terminals of a substrate, such as a semiconductor die or a printed circuit board.
For more complex devices, particularly those requiring a voltage plane, a multilayer TAB tape is used. Rather than having one conductive layer formed on the carrier tape, a conductive layer is formed on each side of the tape. Generally, one conductive layer is used as a voltage plane, for instance a ground plane, while the other conductive layer is used to form a plurality of individual leads. Leads which are designated as ground leads are electrically coupled to the voltage plane by conductive vias which extend through the carrier tape, keeping other leads electrically isolated from the voltage plane.
Use of a ground plane in high performance semiconductor devices is often necessary to lower both self- and mutual inductance created in device leads and to reduce cross-talk by creating a constant characteristic impedance environment for signal leads. Known multilayer TAB tapes such as that described above provide only a limited improvement in lowering lead inductance in a semiconductor device. The effectiveness of utilizing a ground plane in a conventional multilayer TAB tape is restricted by the size, number, and position of the vias used to electrically couple the ground plane and ground leads. To maximize the reduction of inductance, it is desirable to have as many vias as possible, vias which are as large as possible, and vias which are as close to the semiconductor die as possible in order to reduce the ground return loop, thereby effectively lowering inductance. Existing multilayer TAB tapes typically use only three to six vias per ground lead. These vias are restricted in size and position by the width of each lead. While in theory it is desirable to have ground leads as wide as possible to lower inductance, in practice ground lead width is restricted by the need to have a lead density which is as high as possible. Therefore the advantages of high lead count versus low inductance must be compromised with existing multilayer TAB technology.
Apart from providing limited improvement in lowering device inductance, existing multilayer TAB tapes also have a disadvantage with respect to fabrication complexity. Conventional multilayer TAB tapes are processed using additive plating or sequential lamination processes. One possible additive plating process involves plating metal, for example copper, on both sides of a polymer tape. Vias are then formed through one metal layer and through the polymer material to the opposing metal layer by either etching, drilling, or punching operations. The vias are then plated with a conductive material to provide electrical continuity between selected portions of the the two metal layers. Sequential lamination involves laminating a metal foil to each side of a punched polymer tape. Conductive vias are formed by plating through punched, etched, or drilled vias as described above. The punching, etching, drilling, and plating processes required to form the vias are extremely difficult, primarily due to the small geometries involved. Multilayer TAB tape manufacturing has significant yield loss due to the steps required for via formation. The small geometries and complex processes also contribute to reliability problems with the electrical contact between the vias, leads, and ground plane. To the semiconductor device manufacturer, such process complexity results in very high costs for multilayer TAB tapes and raises concerns about the reliability of devices having such tapes.
Therefore, semiconductor manufacturers would benefit from an alternative approach to existing multilayer TAB technology, and more particularly would benefit from an approach which 1) reduces process complexity in manufacturing TAB leadframes by eliminating conductive via formation, thereby lower costs of leadframes to semiconductor manufacturers, and 2) improves device performance by lowering mutual and self-inductance.